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德州仪器GbE用户手册编程手册英文版免费下载
部分目录或截图为：
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KeyStoneArchitectureII
GigabitEthernet(GbE)SwitchSubsystem
forK2EandK2LDevices
Preface.......................................................................................................
1 Introduction.......................................................................................
1.1 Purpose of the Peripheral .................................................................
1.2 Features .....................................................................................
1.3 Gigabit Ethernet Switch Subsystem Functional Block Diagram......................
1.4 Industry Standard(s) Compliance Statement ...........................................
2 Architecture.......................................................................................
2.1 Clock Control................................................................................
2.1.1 Gigabit Switch Subsystem Clock................................................
2.1.2 SGMII SerDes Reference Clock.................................................
2.1.3 MDIO Clock ........................................................................
2.1.4 IEEE 1588 Time Synchronization Clock .......................................
2.1.5 GMII Clock .........................................................................
2.2 Memory Map ................................................................................
2.3 Gigabit Ethernet Switch Architecture ....................................................
2.3.1 Streaming Packet Interface ......................................................
2.3.1.1 Transmit Streaming Packet Interface (Host Port 0 Switch Egress) ..
2.3.1.2 Receive Streaming Packet Interface (Host Port 0 Switch Ingress)...
2.3.2 Media Access Controller Submodule Architecture............................
2.3.2.1 Data Receive Operations ..................................................
2.3.2.2 Data Transmission..........................................................
2.3.3 MAC Receive FIFO Architecture ................................................
2.3.4 Priority Mapping and Transmit VLAN Priority..................................
2.3.5 Statistics Submodule Architecture ..............................................
2.3.5.1 Accessing Statistics Registers ............................................
2.3.5.2 Statistics Interrupts .........................................................
2.3.5.3 Receive Statistics Descriptions ...........................................
2.3.5.4 Transmit (Only) Statistics Descriptions ..................................
2.3.5.5 Receive and Transmit (Shared) Statistics Descriptions ...............
2.3.6 Time Synchronization Submodule Architecture ...............................
2.3.6.1 Time Synchronization Submodule Components........................
2.3.6.2 Time Synchronization Events .............................................
2.3.6.3 Time Synchronization Initialization .......................................
2.3.6.4 Detecting and Processing Time Synchronization Events..............
2.3.7 Address Lookup Engine (ALE) Submodule Architecture.....................
2.3.7.1 ALE Table....................................................................
2.3.7.2 Reading Entries from the ALE Table .....................................
2.3.7.3 Writing Entries to the ALE Table..........................................
2.3.7.4 ALE Table Entry Types ....................................................
2.3.7.5 ALE Packet Forwarding Process .........................................
2.3.7.6 ALE Learning Process......................................................
2.3.8 Error Correction Code (ECC) Submodule Architecture .....................
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