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德州仪器PA2用户手册编程手册英文版免费下载
部分目录或截图为：
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KeyStoneArchitectureII
PacketAccelerator2(PA2)
forK2EandK2LDevices
User'sGuide
Preface .......................................................................
1 Introduction........................................................
1.1 Purpose of the Peripheral .................................
1.2 Features......................................................
1.3 Functional Block Diagram .................................
2 Architecture........................................................
2.1 Clock Control.................................................
2.2 Packet Accelerator 2 Transmit Queue Interface ........
2.3 Programming the Packet Accelerator 2 with Low-Leve
2.4 Packet Accelerator Components ..........................
2.4.1 Cluster Components ...............................
2.4.1.1 Splitter/Combiner Module (SPLITCOMB) .
2.4.1.2 Chunk Data Engine (CDE)..................
2.4.1.3 Packed Data Structure Processor (PDSP
2.4.1.4 Lookup Tables (LUT) ........................
2.4.1.5 Packet Checker Module (CHECKER) .....
2.4.2 Reassembly Engine (RA) Module................
2.4.3 Flexible Statistics Block (FSB) Engine ..........
2.5 Cluster Architecture .........................................
2.5.1 Cluster 0: Ingress 0 Architecture .................
2.5.2 Cluster 1: Ingress 1 Architecture .................
2.5.3 Cluster 2: Ingress 2 Architecture .................
2.5.4 Cluster 3: Ingress 3 Architecture .................
2.5.5 Cluster 4: Ingress 4 Architecture .................
2.5.6 Cluster 5: Post-Classification Architecture ......
2.5.7 Cluster 6: Egress 0 Architecture .................
2.5.8 Cluster 7: Egress 1 Architecture .................
2.5.9 Cluster 8: Egress 2 Architecture .................
2.6 Adding Entries to the Classification Engines ............
2.6.1 Adding Entries to the Classification Engines ...
2.7 DMA Event Support .........................................
2.8 Power Management.........................................
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