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德州仪器Concerto F28M36x用户手册编程手册英文版免费下载
部分目录或截图为：
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ConcertoF28M36x
TechnicalReferenceManual
Preface ..........................................................................................
1 System Control and Interrupts ................................................
1.1 Signal Description ............................................................
1.2 System Control Functional Description ....................................
1.2.1 Device Identification .................................................
1.2.2 Device Configuration Registers ....................................
1.3 Reset Control .................................................................
1.3.1 Device Level Reset Sources .......................................
1.3.2 Handling of Resets at System Level ..............................
1.4 WIR Mode .....................................................................
1.4.1 Entering WIR Mode ..................................................
1.4.2 Exiting WIR Mode ....................................................
1.5 Exceptions and Interrupts Control ..........................................
1.5.1 Master Subsystem Nested Vectored Interrupt Controller .......
1.5.2 Master Subsystem Exceptions Handling ..........................
1.5.3 Master Subsystem Non-Maskable Interrupt (MNMI) Module ...
1.5.4 Control Subsystem PIE .............................................
1.5.5 Control Subsystem Exceptions Handling .........................
1.5.6 Control Subsystem NMI (CNMI) Module ..........................
1.6 Safety Features ...............................................................
1.6.1 Write Protection on Registers ......................................
1.6.2 Missing Clock Detection Logic .....................................
1.6.3 PLLSLIP Detection ...................................................
1.6.4 Control Subsystem PIE Vector Address Validity Check ........
1.6.5 NMIWDs ...............................................................
1.6.6 Watchdog Timers ....................................................
1.6.7 ECC and Parity Enabled RAMs, Shared RAMs Protection .....
1.6.8 ECC Enabled Flash Memory .......................................
1.7 Power Control .................................................................
1.8 Clock Control ..................................................................
1.8.1 Clock Sources ........................................................
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