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德州仪器KeyStone Architecture PSC用户手册编程手册英文版免费下载
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KeyStoneArchitecture
PowerSleepController(PSC)
Preface ..................................................................................
1 Introduction...................................................................
1.1 Purpose of the Peripheral ...........................................
1.2 Terminology Used in This Document ..............................
1.3 Features................................................................
2 Architecture ..................................................................
2.1 Power and Clock Domains ..........................................
2.2 Power Domain and Module States Defined .......................
2.2.1 Power Domain States .......................................
2.2.2 Module States ................................................
2.2.3 Local Reset ...................................................
2.3 Executing State Transitions .........................................
2.3.1 Power Domain State Transitions ..........................
2.3.2 Module State Transitions ...................................
2.3.3 Concurrent Power Domain/Module State Transitions ...
2.3.4 Recommendations for Power Domain/Module Sequenc
2.4 Emulation Support in the PSC.......................................
3 Registers......................................................................
3.1 Power and Sleep Controller (PSC) Register Map.................
3.2 Register Descriptions .................................................
3.2.1 Peripheral Identification Register (PID)....................
3.2.2 Voltage Control Identification Register (VCNTLID) ......
3.2.3 Power Domain Transition Command Register (PTCMD
3.2.4 Power Domain Transition Status Register (PTSTAT) ...
3.2.5 Power Domain Status Register (PDSTATx) ..............
3.2.6 Power Domain Control Register (PDCTLx) ...............
3.2.7 Module Status Register (MDSTATy).......................
3.2.8 Module Control Register (MDCTLy) .......................
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