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德州仪器TMS320F2837xS 用户手册编程手册英文版免费下载
部分目录或截图为：
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TMS320F2837xSDelfinoMicrocontrollers
TechnicalReferenceManual
Preface.........................................................................................
1 C28x Processor....................................................................
1.1 Overview.......................................................................
1.1.1 Floating-Point Unit ..................................................
1.1.2 Trigonometric Math Unit ...........................................
1.1.3 Viterbi, Complex Math, and CRC Unit II (VCU-II) ..............
2 System Control ....................................................................
2.1 Introduction....................................................................
2.2 System Control Functional Description....................................
2.2.1 Device Identification ................................................
2.2.2 Device Configuration Registers ...................................
2.3 Resets .........................................................................
2.3.1 Reset Sources .......................................................
2.3.2 External Reset (XRS) ...............................................
2.3.3 Power-On Reset (POR) ............................................
2.3.4 Debugger Reset (SYSRS) .........................................
2.3.5 Watchdog Reset (WDRS) ..........................................
2.3.6 NMI Watchdog Reset (NMIWDRS) ...............................
2.3.7 DCSM Safe Code Copy Reset (SCCRESET) ...................
2.3.8 Hibernate Reset (HIBRESET) .....................................
2.3.9 Hardware BIST Reset (HWBISTRS)..............................
2.3.10 Test Reset (TRST) .................................................
2.4 Peripheral Interrupts .........................................................
2.4.1 Interrupt Concepts...................................................
2.4.2 Interrupt Architecture................................................
2.4.3 Interrupt Entry Sequence...........................................
2.4.4 Configuring and Using Interrupts..................................
2.4.5 PIE Channel Mapping ..............................................
2.4.6 Vector Tables ........................................................
2.5 Exceptions and Non-Maskable Interrupts.................................
2.5.1 Configuring and Using NMIs .......................................
2.5.2 Emulation Considerations ..........................................
2.5.3 NMI Sources .........................................................
2.5.4 Illegal Instruction Trap (ITRAP)....................................
2.6 Safety Features...............................................................
2.6.1 Write Protection on Registers......................................
2.6.2 Missing Clock Detection Logic.....................................
2.6.3 PLLSLIP Detection ..................................................
2.6.4 CPU1 Vector Address Validity Check ............................
2.6.5 NMIWDs ..............................................................
2.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection...
2.6.7 ECC Enabled Flash Memory ......................................
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