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德州仪器TMS320DM814x DaVinci Digital Video Processors用户手册编程手册英文版免费下载
部分目录或截图为：
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TMS320DM814xDaVinci
DigitalVideoProcessors
TechnicalReferenceManual
Preface ............................................................................................
1 Chip Level Resources .............................................................
1.1 ARM® Cortex™-A8 Microprocessor Unit (MPU) Subsystem Overview .
1.1.1 ARM Cortex-A8 RISC Processor ....................................
1.1.2 Embedded Trace Module (ETM) .....................................
1.1.3 ARM Cortex-A8 Interrupt Controller (AINTC) ......................
1.1.4 ARM Cortex-A8 PLL (PLL_ARM) ....................................
1.1.5 ARM MPU Interconnect ...............................................
1.2 Media Controller Subsystem ..................................................
1.2.1 Dual Cortex-M3 MPU Subsystem Overview ........................
1.2.2 Dual Cortex-M3 MPU Subsystem Integration ......................
1.2.3 Dual Cortex-M3 MPU Subsystem Functional Description ........
1.2.4 Shared Cache ..........................................................
1.2.5 Shared Cache MMU ...................................................
1.2.6 L2 MMU .................................................................
1.2.7 Registers ................................................................
1.3 C674x DSP ......................................................................
1.3.1 Introduction .............................................................
1.3.2 TMS320C674x Megamodule .........................................
1.3.3 Memory Map ............................................................
1.3.4 Advanced Event Triggering (AET) ...................................
1.4 HD Video Coprocessor Subsystem ...........................................
1.4.1 HDVICP2 Overview ....................................................
1.4.2 ICONTs ..................................................................
1.4.3 vDMA ....................................................................
1.4.4 iME3 .....................................................................
1.4.5 iPE3 ......................................................................
1.4.6 MC3 ......................................................................
1.4.7 CALC3 ...................................................................
1.4.8 iLF3 ......................................................................
1.4.9 ECD3 ....................................................................
1.4.10 SL2 Interface ..........................................................
1.4.11 Message Bus ..........................................................
1.4.12 HDVICP2 Local Interconnect ........................................
1.4.13 MailBox .................................................................
1.4.14 HDVICP2 System Control ...........................................
1.5 System MMU ....................................................................
1.5.1 MMU Overview .........................................................
1.5.2 MMU Integration .......................................................
1.5.3 MMU Functional Description .........................................
1.5.4 MMU Low-level Programming Models ..............................
1.5.5 MMU Registers .........................................................
1.6 SGX530 Graphics Subsystem .................................................
1.6.1 SGX Overview ..........................................................
1.6.2 SGX Integration ........................................................
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