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德州仪器AM387xSitara ARM Processors用户手册编程手册英文版免费下载
部分目录或截图为：
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AM387xSitara
ARMProcessors
TechnicalReferenceManual
Preface ..........................................................................................
1 Chip Level Resources ...........................................................
1.1 ARM® Cortex™-A8 Microprocessor Unit (MPU) Subsystem Overview
1.1.1 ARM Cortex-A8 RISC Processor ..................................
1.1.2 Embedded Trace Module (ETM) ...................................
1.1.3 ARM Cortex-A8 Interrupt Controller (AINTC) ....................
1.1.4 ARM Cortex-A8 PLL (PLL_ARM) ..................................
1.1.5 ARM MPU Interconnect .............................................
1.2 Media Controller Subsystem ................................................
1.2.1 Dual Cortex-M3 MPU Subsystem Overview ......................
1.2.2 Dual Cortex-M3 MPU Subsystem Integration ....................
1.2.3 Dual Cortex-M3 MPU Subsystem Functional Description ......
1.2.4 Shared Cache ........................................................
1.2.5 Shared Cache MMU .................................................
1.2.6 L2 MMU ...............................................................
1.2.7 Registers ..............................................................
1.3 C674x DSP ....................................................................
1.3.1 Introduction ...........................................................
1.3.2 TMS320C674x Megamodule .......................................
1.3.3 Memory Map ..........................................................
1.3.4 Advanced Event Triggering (AET) .................................
1.4 System MMU ..................................................................
1.4.1 MMU Overview .......................................................
1.4.2 MMU Integration .....................................................
1.4.3 MMU Functional Description .......................................
1.4.4 MMU Low-level Programming Models ............................
1.4.5 MMU Registers .......................................................
1.5 SGX530 Graphics Subsystem ...............................................
1.5.1 SGX Overview ........................................................
1.5.2 SGX Integration ......................................................
1.5.3 SGX Functional Description ........................................
1.5.4 SGX Register Manual ...............................................
1.6 Device Interrupts and EDMA Events .......................................
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