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德州仪器AM389xSitara ARM Processors用户手册编程手册英文版免费下载
部分目录或截图为：
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AM389xSitara
ARMProcessors
TechnicalReferenceManual
Preface ....................................................................
1 Chip Level Resources ......................................
1.1 Introduction ...............................................
1.2 MPU Subsystem .........................................
1.2.1 Introduction ......................................
1.2.2 Features ..........................................
1.2.3 MPU Subsystem Integration ...................
1.2.4 MPU Subsystem Clock and Reset Distributio
1.2.5 ARM Subchip ....................................
1.2.6 AXI2OCP and I2Async Bridges ...............
1.2.7 Interrupt Controller ..............................
1.2.8 Power Management ............................
1.2.9 Host ARM Address Map .......................
1.2.10 ARM Programming Model ....................
1.3 Memory Map Summary .................................
1.3.1 L3 Memory Map .................................
1.3.2 L4 Memory Map .................................
1.3.3 TILER Extended Addressing Map ............
1.3.4 Cortex™-A8 Memory Map .....................
1.4 System MMU .............................................
1.4.1 MMU Overview ..................................
1.4.2 MMU Integration ................................
1.4.3 MMU Functional Description ..................
1.4.4 MMU Low-level Programming Models .......
1.4.5 MMU Registers ..................................
1.5 SGX530 Graphics Subsystem ..........................
1.5.1 SGX Overview ...................................
1.5.2 SGX Integration .................................
1.5.3 SGX Functional Description ...................
1.5.4 SGX Registers ...................................
1.6 Device Interrupts .........................................
1.6.1 Interrupt Requests to Cortex-A8 MPU INTC
1.7 EDMA and EDMA Events ...............................
1.7.1 Overview .........................................
1.7.2 EDMA Regions ..................................
1.7.3 Synchronization Events ........................
1.8 Device Clocking and Flying Adder PLL ...............
1.8.1 Overview .........................................
1.8.2 I/O Domains .....................................
1.8.3 Flying Adder PLL ................................
1.8.4 Clock Out .........................................
1.9 Bus Interconnect .........................................
1.9.1 Terminology ......................................
1.9.2 L3 Interconnect ..................................
1.10 Inter-Processor Communication .......................
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