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德州仪器RM57LxHercules用户手册安全手册英文版免费下载
部分目录或截图为：
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SafetyManualforRM57LxHercules™ARM®
SafetyCriticalMicrocontrollers
User'sGuide
1 Introduction ..............................................................................
2 Hercules RM57Lx Product Overview.............................................
2.1 Targeted Applications..........................................................
2.2 Product Safety Constraints ...................................................
3 Hercules Development Process for Management of Systematic Faul
3.1 TI Standard MCU Automotive Development Process .....................
3.2 TI MCU Automotive Legacy IEC 61508 Development Process ..........
3.3 Yogitech fRMethodology Development Process ...........................
3.4 Hercules Enhanced Safety Development Process.........................
4 Hercules Product Architecture for Management of Random Faults...
4.1 Safe Island Philosophy and Architecture Partition for Safety Analysis ..
4.2 Management of Family Variants ..............................................
4.3 Operating States ................................................................
4.4 Management of Errors .........................................................
5 Hercules Architecture Safety Mechanisms and Assumptions of Use
5.1 Power Supply ...................................................................
5.2 Power Management Module (PMM) .........................................
5.3 Clocks ............................................................................
5.4 Reset .............................................................................
5.5 System Module .................................................................
5.6 Error Signaling Module (ESM) ...............................................
5.7 CPU Subsystem ................................................................
5.8 Primary Embedded Flash .....................................................
5.9 Flash EEPROM Emulation (FEE) ............................................
5.10 Primary Embedded SRAM ....................................................
5.11 Memory Interconnect...........................................................
5.12 Main Peripheral Interconnect .................................................
5.13 Peripheral Interconnect Segment 1 ..........................................
5.14 Peripheral Interconnect Segment 2 ..........................................
5.15 Peripheral Interconnect Segment 3 ..........................................
5.16 EFuse Static Configuration....................................................
5.17 OTP Static Configuration ......................................................
5.18 I/O Multiplexing (IOMM) .......................................................
5.19 Vectored Interrupt Module (VIM) .............................................
5.20 Real Time Interrupt (RTI) ......................................................
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